--
-- Clock generator
-- Modified from http://hdllib.at.infoseek.co.jp/hdl/vhdl/ttl1.html
--

LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
USE IEEE.STD_LOGIC_1164_EXTENSIONS.ALL ;

ENTITY clkgen IS
    GENERIC (
        half_cycle : integer := 25
        );
    PORT (
        clk  :   OUT STD_ULOGIC
         ) ;
END clkgen ;

ARCHITECTURE clkgen of clkgen IS
    SIGNAL  clk_tmp : STD_ULOGIC := '0' ;
BEGIN
    clk_tmp <= NOT clk AFTER 25 ns;
    clk <= clk_tmp;
END clkgen;
